A phase locked loop (PLL) is a circuit that locks the phase of an output signal to the phase of a reference signal. A PLL operates as a feedback system that feeds the output signal back to a phase detector, which detects a phase error in the output signal and then drives an oscillator to adjust the phase of the output signal in response to the detected phase error.
PLLs are configured to operate in two states, an unlocked or settling state and a locked or settled state. In the unlocked state, the phase detector generates a control signal that changes the frequency of the oscillator so that the phase of the output signal converges upon the phase of the reference signal. In the locked state, the phase detector generates a control signal that keeps the phases of the reference signal and the output signal together.